RAIDR is an intelligent method of adapting the DRAM memory refresh time to the refresh rate profile data of DRAM cells, which varies due to process variations. This allows the refresh rate not to remain constant i.e. determined by the weakest DRAM cell, but now it varies across the DRAM for different ‘Bins’. Based on the refresh rate of DRAM cells, the mechanism groups the DRAM cell rows into retention time bins, which is implemented using the Bloom filters implemented in the memory controller (low area overhead and no overflows). Bins with Weak DRAM cells, get refreshed more often than the one with good DRAM Cells.
Why this problem is important to deal with?
- The refresh rate causes power consumption to increase.
- Memory cannot be accessed during refresh i.e. denial of service.
- Scaling the size of memory would increase the problem of refresh rate.
- Only less than 1000 cells (out of 10e11) require refresh less than 256ms refresh, still the complete memory is refreshed every 64ms.
Strengths of paper and mechanisms
- With only 2 retention time bins (1.25 KB) implemented in the memory controller, there is a 74.6% refresh reduction, 16.1% average DRAM power reduction, and 8.6% average system performance improvement.
Weaknesses of paper and mechanism
- DRAM Cells store data in Capacitors. Over time, the capacitor loses charge. Therefore, data stored in DRAM is periodically read-out and rewritten, This is called DRAM Memory Refresh.
Ideas for improvement
Reference: Liu, Jamie, et al. “RAIDR: Retention-aware intelligent DRAM refresh.” ACM SIGARCH Computer Architecture News 40.3 (2012): 1-12.